1. Field of the Invention
The present invention relates to the field of digital memory modules and more specifically it relates to means for transmitting data and control signals onto individual lines in the memory interface buss.
2. Background Art
Digital memory modules such as used in computers, printers, and telecommunications equipment are clocked devices that must communicate data, control, and status signals onto a memory buss. The signals are digital signals that are typically switched synchronously with the memory clock. Following a clocked transition, signals require a period of time to stabilize and allow switching transients to die off before their signal state can be considered “valid”. The time difference between the time of signal stabilization and the start of the subsequent clocked transitioning minus the time required by the system to receive the valid information comprises the timing margin of the memory.
Historically, timing margin (as well as power consumption) has not represented a major problem with memory modules. When more than one signal was to be coupled onto a single line in the memory buss, memory buss driver outputs were connected together as the simplest and lowest cost method for driving the memory buss, because timing margin was not a concern. An example prior art configuration is illustrated in FIG. 1. Signals A and B are coupled to node 100 through buffers U100 and U101 respectively. The output of node 100 is strobed for A or B as desired.
With the increasing need for higher speed memory, timing margin can no longer be ignored. The combined transition and stabilization time now represents a significant portion of, if not the entire, clock period. Since transition times and time delays are subject to manufacturing variability, timing margin has become both small and widely variable. This makes for low yield production and very costly memory modules.
In addition to the timing margin problem, the trend has been toward larger and larger capacity memory modules. The transition period with associated high current draw has resulted in a major power consumption/distribution problem for state of the art memory modules. One of the major sources for high power consumption is the use of simple wired-OR connections of multiple line driver outputs driving the memory buss. During transitions, both upper and lower type switching devices within the line drivers attached to an individual line in the buss can be “on” or partially “on”. This results in high transient current flow and resulting high power dissipation. At high memory clock rates, this represents a high “duty cycle” that will only become worse with increasing memory clock rates in the future. For large memory modules, there are such a large number of the transitions occurring at a typical clocked transition that the total power consumption is large and difficult to deal with given conventional memory module to motherboard interfacing.
As a result, it would be extremely desirable to have digital memory to memory buss interface circuitry that would provide adequate timing margin for memory modules at higher clock frequencies while reducing the total power consumption associated with the present buss interface.